The present invention relates to differential circuit timing modeling and, more specifically, to deterministic and statistical timing modeling for differential circuits and to the generation of deterministic and statistical timing macro-models for differential circuits.
Static timing analysis (STA) relates to the computation and propagation of expected timing values of an integrated circuit (IC) before the physical fabrication process of a chip. The results of STA are used to predict whether or not the design will meet all the timing requirements or constraints for proper functionality.
Synchronous high-performance ICs have traditionally been characterized by a clock frequency at which they operate. Gauging the ability of a circuit to operate at the specified speed requires measurement, during the design process, of its delay at numerous steps. Moreover, delay calculations must be incorporated into the inner loop of timing optimizers at various phases of design, such as logic synthesis, layout (placement and routing) and in in-place optimizations performed late in the design cycle. While such timing measurements can theoretically be performed using a rigorous circuit simulation, such an approach is liable to be too slow to be practical. Instead, timing modeling plays a vital role in facilitating fast and reasonably accurate measurements of circuit timing where a timing macro-model encapsulates the relevant timing information in a compact form that was generated from the STA of the original design. The speedup comes from the simple but accurate timing models.
In a synchronous digital system, data is supposed to move in lockstep, advancing one stage on each tick of the clock signal. This is enforced by synchronizing elements such as flip-flops or latches, which copy their input to their output when instructed to do so by the clock. Only two kinds of timing errors are possible in such a system. These include a setup time violation, when a signal arrives too late, and misses the time when it should advance, and a hold time violation, when an input signal changes too soon after the clock's active transition. The time when a signal arrives can vary due to many reasons such as the input data varying, the circuit performing different operations, temperature and voltage changes and manufacturing differences in exact constructions of each circuit part. The main goal of timing analysis is to verify that despite these possible variations, all signals will arrive neither too early nor too late and hence proper circuit operation can be assured.